Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed “Moore's Law.” Moore's Law dictates that the number of electronic devices which will fit on an integrated circuit doubles every two years. Today's wafer fabrication facilities are routinely producing 65 nm and 45 nm feature size devices on 300 mm wafers. Fabrication facilities are already being planned incorporating even smaller design rules on 450 mm wafers.
As device feature sizes become smaller and integration density increases, issues not previously considered crucial by the semiconductor industry are becoming of greater concern. For example, process tools must be increasingly capable of handling large wafer sizes with extremely small features designed and fabricated thereon. Additionally, the process tools must function properly in a high vacuum environment containing highly corrosive gases and frequently operating in a plasma. These challenging issues must also be met in a tool with increasingly demanding values of metrics such as mean-time-to-failure (MTTF), mean-time-to-clean (MTTC), and mean-time-to-repair (MTTR).
One of the primary steps in fabricating modern semiconductor devices is forming various layers, including dielectric layers and metal layers, on a semiconductor substrate. As is well known, these layers can be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In a conventional thermal CVD process, reactive gases are supplied to the substrate surface where heat-induced chemical reactions (homogeneous or heterogeneous) take place to produce a desired film. In a plasma-enhanced CVD (PECVD) process, a controlled plasma is formed to decompose and/or energize reactive species to produce the desired film.
In general, reaction rates in thermal and plasma processes may be controlled by controlling one or more of the following: temperature, pressure, plasma density, reactant gas flow rate, power frequency, power levels, chamber physical geometry, and others. In an exemplary PVD system, a target (a plate of the material that is to be deposited) is connected to a negative voltage supply (direct current (DC) or radio frequency (RF)) while a substrate holder facing the target is either grounded, floating, biased, heated, cooled, or some combination thereof. A gas, such as argon, is introduced into the PVD system, typically maintained at a pressure between a few millitorr (mtorr) and about 100 mtorr, to provide a medium in which a glow discharge can be initiated and maintained. When the glow discharge is started, positive ions strike the target, and target atoms are removed by momentum transfer. These target atoms subsequently condense into a thin film on the substrate, which is on the substrate holder. Thus, coupling of RF energy ((e.g., 400 KHz, 2 MHz, 13.56 MHz, etc.) to various electrically conductive surfaces in a vacuum environment, such as electrostatic chucks and plasma containment liners, is critically important.
Additionally, silicon etch applications are extremely critical because they may be used to form, for example, transistor gates, the outcome of which determines the performance of the finished device. As a result, gate etch carries stringent process requirements for critical dimension (CD) uniformity, defectively, and micro-loading in isolated and dense areas. In addition, in-situ processing capability and applications, such as shallow trench isolation (STI) and spacer formation, require a large process window. In situ processing enables advanced applications such as STI etch, and increases the efficiency of gate etch when backside antireflective coating (BARC) and mask open as well as the main etch are performed in the same chamber. In-situ processing increases productivity, requiring fewer processing steps, reducing wafer moves, and lowering transfer overhead.
Increasingly stringent requirements for fabricating these high integration devices are needed and conventional processing tools and associated components used both in and with the tools are becoming inadequate to meet these requirements. Additionally, as device designs evolve, more advanced capabilities are required process tools to implement these devices. For example, components and mechanisms forming various process tools must be increasingly robust in increasingly hostile operating environments.